The present invention relates to electronic timing generation, and more particularly to a technique for reducing lock time of a phase locked loop (PLL).
In electronic systems that use phase locked loops (PLL) for generating a clock or other synchronized timing signal, the time required for the PLL to achieve lock is usually important to its operation. Therefore most PLLs are designed to meet a maximum allowable lock time specification, also known as switching speed. The time for a PLL to achieve lock is dependent upon a number of factors, such as the PLL""s loop bandwidth, damping factor, frequency step size, etc. Since some of these parameters are constrained by other system requirements, system performance tradeoffs are generally necessary. Depending upon the system""s performance requirements, a single PLL may not be able to simultaneously meet all the specifications and more complex, costly designs using multiple PLLs may be required.
FIG. 1 shows alternative prior art phase lock loops. The conventional PLL has a reference signal source, or oscillator, the output of which is input to a phase detector. Also input to the phase detector is the output of a voltage controlled oscillator (VCO) via a frequency divider. The difference in frequency between the reference signal source and the VCO output is provided by the phase detector to a loop filter. The output from the loop filter is a control signal applied to the VCO to adjust the VCO output frequency.
This basic PLL configuration works well for applications that tune over narrow frequency ranges and/or do not have demanding low phase noise requirements. When the PLL must tune over a wide frequency range and the PLL""s phase noise performance is also critical, the circuit configuration shown in FIG. 1 is often used. The VCO""s fine and coarse tune ports may be two physically separate terminals on the VCO, or they may be implemented using a resistive voltage divider network ahead of the VCO with only a single tune port. The fine tune port has a low tuning sensitivity, necessary to achieve good phase noise and spurious performance, and is controlled by the behavior of the feedback circuit of the closed-loop control system. It is responsible for maintaining the PLL in phase-lock. Since the fine tune port has low tuning sensitivity, the capture and hold-in range is small, and hence the VCO must be tuned close to the desired operating frequency using the VCO""s coarse tune port. In a wide tuning PLL the tuning sensitivity of the coarse tuning port is high. The coarse tune voltage is typically derived from a digital to analog converter and is usually filtered by a very long time-constant RC filter to prevent noise injection into the PLL. A distinct limitation of this architecture is that, whenever it is desired to lock the PLL to a new frequency or when the PLL is first turned on, the large filter capacitor must be charged sufficiently close to the proper value for the fine tune port to capture control and achieve phase lock. Since the rate of change of voltage across the filter capacitor diminishes as the capacitor charges/discharges towards its final value, the time to achieve phase lock may be excessively long. In some instances the lock time may be improved by adding speed-up circuitry, shown in dotted lines in FIG. 1. An electronic switch may be used to reduce the RC time constant while the capacitor is charging. The switch then opens to increase the filtering after the PLL has locked. One disadvantage of this approach is that low resistance electronic switches with high current carrying capacity, good OFF isolation and small size are expensive. Also charge injection when the switch is turned OFF may momentarily upset the loop, and additional driver circuitry may be required to control the switch. In FIG. 2 the electronic switch is replaced with diodes to shunt a low value resistor across the filter when the capacitor needs to be charged or discharged. This circuit works well for large changes in coarse tune voltage, but eventually when the voltage differential between the output of the DAC and the capacitor is less than a diode drop, approximately 0.65 volts, the diode becomes open circuited and the shunt resistor is rendered ineffective. This circuit results in significant lock times, especially when the coarse tune sensitivity is a couple of hundred MHz per volt and the fine tuning port has a narrow tuning range, which may be only several hundred kHz for good spurious and noise performance. The filter still has to charge with a relatively long time constant until the VCO is tuned within the range to achieve lock.
What is desired is a technique for reducing lock up time of a PLL when other system constraints are inconsistent with achieving fast switching speed.
According the present invention provides a phase locked loop with reduced lock time by having an operational amplifier amplify a differential voltage across a filter resistor of an RC noise filter, the RC noise filter being used to couple a coarse tune voltage to a VCO in the phase locked loop. The amplified differential voltage is coupled to the bases of a pair of opposite polarity transistors to turn ON one of the transistors, which in turn rapidly charges/discharges a filter capacitor of the RC noise filter until the charge on the filter capacitor closely approximates the applied coarse tune voltage. Alternatively the amplified differential voltage may be applied to a pair of parallel, opposite polarity diodes coupled to rapidly charge/discharge the filter capacitor.
The objects, advantages and other novel features of the present invention are apparent from the following detailed description when read in conjunction with the appended claims and attached drawing.